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1 multiphase pwm regulator for amd fusion? desktop cpus using svi 2.0 isl62773 the isl62773 is fully compliant with amd fusion? svi 2.0 and provides a complete solution for desktop microprocessor and graphics processor core power. the isl62773 controller supports two voltage regulators (vrs) with three integrated gate drivers and two optional external drivers for maximum flexibility. the core vr can be configured for 3-, 2-, or 1-phase operation while the northbridge vr supports 2- or 1-phase configurations. the two vrs share a serial control bus to communicate with the amd cpu and achieve lower cost and smal ler board area compared with two-chip solutions. the pwm modulator is based on intersil?s robust ripple regulator (r3) technology?. comp ared to traditional modulators, the r3 modulator can automatically change switching frequency for faster transient settling ti me during load transients and improved light load efficiency. the isl62773 has several other key features. both outputs support dcr current sensing with single ntc thermistor for dcr temperature compensation or accurate resistor current sensing. both outputs utilize re mote voltage sense, adjustable switching frequency, oc protection and power-good. applications ? amd fusion cpu/gpu core power ?desktop computers features ? supports amd svi 2.0 serial data bus interface ? dual output controller with integrated drivers - two dedicated core drivers - one programmable driver for either core or northbridge ? precision voltage regulation - 0.5% system accuracy over-temperature - 0.5v to 1.55v in 6.25mv steps - enhanced load line accuracy ? supports multiple current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? programmable 1-, 2- or 3-phase for the core output and 1- or 2-phase for the northbridge output ? adaptive body diode conduction time reduction ? superior noise immunity and transient response ? output current monitor and thermal monitor ? differential remote voltage sensing ? high efficiency across entire load range ? programmable slew rate, vid offset, droop, and switching frequency on both outputs ? ocp/woc, ovp, pgood, and thermal monitor ? small footprint 48 ld 6x6 qfn package - pb-free (rohs compliant) core performance figure 1. efficiency vs load figure 2. v out vs load 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) efficiency (%) v out core = 1.1v v in = 8v v in = 12v v in = 19v 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 0 5 10 15 20 25 30 35 40 45 50 55 i out (a) v out (a) v in = 8v v in = 12v v in = 19v v out core = 1.1v fn8263.0 march 7, 2012 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) and r3 technology are trademarks ow ned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl62773 2 march 7, 2012 fn8263.0 simplified application circuit for high power cpu core nb_ph1 nb_ph2 figure 3. typical application circuit using inductor dcr sensing bootx ugatex phasex lgatex boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm_y isl62773 isump isumn ph1 ph2 ph3 vo1 vo2 vo3 gnd pad fb_nb comp_nb vsen_nb vnb_sense vddp pgood isen1 isen2 isen3 enable ph1 ph2 ph3 vcore ph2 isl6208 vo2 vo1 vin vo3 ph1 vin vin vo1 ph3 ph1 vin vnb vdd pwm2_nb isl6208 vnb1 nb_ph1 vnb2 nb_ph2 isen1_nb isen2_nb isump_nb isumn_nb nb_ph1 nb_ph2 vnb1 vnb2 ntc_nb imon imon_nb pwrok svt svd p svc vddio ntc vr_hot_l thermal indicator fccm_nb vcore_sense fb comp vsen rtn fb2 vin vin ntc ntc cn cn ri ri
isl62773 3 march 7, 2012 fn8263.0 simplified application circuit with 3 internal drivers used for core figure 4. typical application circuit using inductor dcr sensing bootx ugatex phasex lgatex boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 isl62773 gnd pad vcore_sense fb_nb comp_nb vsen_nb vnb_sense vddp pgood enable vcore ph2 isl6208 vo2 vo1 vin vnb1 ph1 vin vin vo1 nb_ph1 ph1 vin vnb vdd pwm2_nb isl6208 v03 ph3 vnb2 nb_ph2 ntc_nb imon imon_nb pwrok svt svd p svc vddio ntc vr_hot_l thermal indicator fb comp vsen rtn fb2 fccm_nb pwm_y vin nb_ph1 nb_ph2 isen1_nb isen2_nb isump_nb isumn_nb nb_ph1 nb_ph2 vnb1 vnb2 isump isumn ph1 ph2 ph3 vo1 vo2 vo3 isen1 isen2 isen3 ph1 ph2 ph3 vin ntc ntc cn cn ri ri
isl62773 4 march 7, 2012 fn8263.0 simplified application circuit for mid-power cpus [2+1 configuration] figure 5. typical application circuit using resistor sensing bootx ugatex phasex lgatex boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm2_nb isl62773 isump isumn vp1 vp2 vn1 vn2 gnd pad fb_nb comp_nb vsen_nb vnb_sense vddp pgood isen1 isen2 isen3 enable vp1 vp2 vcore vp2 vn2 vin vin vnb vdd pwm_y isl6208 nbn nbp ntc_nb imon imon_nb pwrok svt svd p svc vddio ntc vr_hot_l thermal indicator fccm_nb vcore_sense fb comp vsen rtn fb2 vin +5v +5v isen1_nb isen2_nb isump_nb isumn_nb nbp nbn 10kw* vin open ntc ntc * resistor required or isen1_nb will pull high if left open and disable channel 1. open open open open vp1 vn1 cn cn ri ri
isl62773 5 march 7, 2012 fn8263.0 simplified application circuit for low power cpus [1+1 configuration] figure 6. typical application circuit using inductor dcr sensing bootx ugatex phasex lgatex boot2 ugate2 phase2 lgate2 boot1 ugate1 phase1 lgate1 pwm_y isl62773 isump isumn vo1 gnd pad vddp pgood isen1 isen2 isen3 enable vcore vo1 ph1 vin vo1 ph1 vin vnb vdd pwm2_nb vnb1 nb_ph1 isen1_nb isen2_nb isump_nb isumn_nb nb_ph1 vnb1 +5v open open open open imon imon_nb pwrok svt svd p svc vddio ntc vr_hot thermal indicator fb_nb comp_nb vsen_nb vnb_sense +5v vcore_sense fb comp vsen rtn fb2 +5v fccm_nb open open open ntc_nb ph1 vin ntc ntc 10kw* * resistor required or isen1_nb will pull high if left open and disable channel 1. 10kw* * resistor required or isen1_nb will pull high if left open and disable channel 1. cn cn ri ri
isl62773 6 march 7, 2012 fn8263.0 block diagram rtn ? e/a fb idroop current sense isump isumn comp driver driver lgate1 phase1 ugate1 boot1 vccp ov fault pgood _ + _ + + + driver driver lgate2 phase2 ugate2 boot2 ibal fault oc fault pwm_y isen3 isen2 isen1 current balancing digital interface pwrok svc svd driver driver lgatex phasex ugatex bootx ov fault pgood_nb core_i dac1 nb_i dac2 temp monitor ntc_nb ntc vr_hot_l t_monitor offset freq slewrate config prog enable telemetry d/a a/d idroop idroop_nb rtn 6 e/a fb_nb idroop_nb current sense isump_nb isumn_nb comp_nb vr2 modulator _ + _ + + + vr1 modulator fb2 circuit vdd gnd isen1_nb isen2_nb current balancing ibal fault pwm2_nb svt floating driver & pwm config logic oc fault fb2 current a/d imon imon_nb vsen vsen vddio core_i nb_i core_v nb_v nb_v voltage a/d core_v voltage a/d
isl62773 7 march 7, 2012 fn8263.0 pin configuration isl62773 (48 ld qfn) top view isen1_nb isump_nb isumn_nb vsen_nb 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 fb_nb comp_nb pgood_nb fccm_nb pwm2_nb lgatex phasex ugatex isen3 isen2 isen1 isump isumn vseb fb2 fb pgood boot1 bootx vin boot2 ugate2 phase2 lgate2 vddp vdd pwm_y lgate1 phase1 ugate1 isen2_nb ntc_nb imon_nb svc vr_hot_l svd vddio svt enable pwrok imon ntc comp rtn gnd pad (bottom) pin descriptions pin number symbol description 1 isen2_nb individual current sensing for channel 2 of the northbridge vr. when isen2_nb is pulled to +5v, the controller will disable channel 2 and the northbridge vr will run single-phase. 2 ntc_nb thermistor input to vr_hot_l circuit to monitor northbridge vr temperature. 3 imon_nb northbridge output cu rrent monitor. a current proportional to the northbridge vr output current is sourced from this pin. 4svc serial vid clock input from the cpu processor master device. 5 vr_hot_l thermal indicator signal to amd cpu. therma l overload open drain output indicator active low. 6 svd serial vid data bi-directional signal from the cpu processor master device to the vr. 7 vddio vddio is the processor memory interface power rail an d this pin serves as the reference to the controller ic for this processor i/o signal level. 8 svt serial vid telemetry (svt) data line input to the cpu from the controller ic. telemetry and vid-on-the-fly complete signal provided on from this pin. 9 enable enable input. a high level lo gic on this pin enables both vrs. 10 pwrok system power good input. when this pin is high, the svi 2 interface is active and the i 2 c protocol is running. while this pin is low, the svc and svd in put states determine the pre-pwrok metal vid. this pin must be low prior to the isl62773 pgood outp ut going high per the amd svi 2.0 controller guidelines. 11 imon core output current monitor. a current proportional to the core vr output current is sourced from this pin. 12 ntc thermistor input to vr_hot_l circuit to monitor core vr temperature. 13 isen3 isen3 is the individual current sensing for channel 3. when isen3 is pulled to +5v, the controller disables channel 3, and the core vr runs in two-phase mode.
isl62773 8 march 7, 2012 fn8263.0 14 isen2 individual current sensing for channel 2 of the core vr. when isen2 is pulled to +5v, the controller disables channel 2, and the core vr runs in single-phase mode. 15 isen1 individual current sensing for channel 1 of the core vr. if isen2 is tied to +5v , this pin cannot be left open and must be tied to gnd with a 10k ? resistor. if isen1 is tied to +5v , the core portion of the ic is shutdown. 16 isump non-inverting input of the transconductance amplif ier for current monitor and load line of core output. 17 isumn inverting input of the transconductance amplifie r for current monitor and load line of core output. 18 vsen output voltage sense pin for the core controller. connect to the +sense pin of the microprocessor die. 19 rtn output voltage sense return pin for both core vr and northbridge vr . connect to the -sense pin of the microprocessor die. 20 fb2 there is a switch between the fb2 pin and the fb pi n. the switch is on in 2-phase or 3-phase mode and is off in 1-phase mode. the components connecting to fb2 are used to adjust the compensation in 1- phase mode of the core vr to achieve optimum performance 21 fb output voltage feedback to the inverting input of the core controller error amplifier. 22 comp core controller error amplifier output. a resistor from comp to gnd sets the core vr offset voltage. 23 pgood open-drain output to indicate the core portion of the ic is ready to supply regulated voltage. pull up externally to vdd or 3.3v through a resistor. 24 boot1 connect an mlcc capacitor across the boot1 an d the phase1 pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the boot1 pin, each time the phase1 pin drops below vddp minus the voltage dropped across the internal boot diode. 25 ugate1 output of the phase 1 high-side mosfet gate driv er of the core vr. connect the ugate1 pin to the gate of the phase 1 high-side mosfet(s). 26 phase1 current return path for the phase 1 high-side mosf et gate driver of vr1. connect the phase1 pin to the node consisting of the high-side mo sfet source, the low-side mosfet drain, and the output inductor of phase 1. 27 lgate1 output of the phase 1 low-side mosfet gate driv er of the core vr. connect the lgate1 pin to the gate of the phase 1 low-side mosfet(s). 28 pwm_y floating pwm output used for either channel 3 of the core vr or channel 1 of the northbridge vr depending on the fccm_nb resistor connected between fccm_nb and gnd. 29 vdd 5v bias power. a resistor [2 ? ] and a decoupling capacitor should be used from the +5v supply. a high quality, x7r dielectric mlcc capacitor is recommended. 30 vddp input voltage bias for the internal gate drivers. connect +5v to the vddp pin. decouple with at least 1f of capacitance to gnd. a high quality, x7r dielectric mlcc capacitor is recommended. 31 lgate2 output of the phase 2 low-side mosfet gate driv er of the core vr. connect the lgate2 pin to the gate of the phase 2 low-side mosfet(s). 32 phase2 current return path for the phase 2 high-side mo sfet gate driver of the core vr. connect the phase2 pin to the node consisting of the high-side mosfet source, the low-si de mosfet drain, and the output inductor of phase 2. 33 ugate2 output of the phase 2 high-side mosfet gate driv er of the core vr. connect the ugate2 pin to the gate of the phase 2 high-side mosfet(s). 34 boot2 connect an mlcc capacitor across the boot2 and phase2 pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the boot2 pin, each time the phase2 pin drops below vddp minus the voltage dropped across the internal boot diode. 35 vin battery supply voltage, used for feed-forward. 36 bootx boot connection of the programmable internal driver used for either channel 3 of the core vr or channel 1 of the northbridge vr based on the conf iguration state selected by the fccm_nb resistor. connect an mlcc capacitor across the boot1x and th e phasex pins. the boot capacitor is charged, through an internal boot diode connected from the vddp pin to the bootx pin, each time the phasex pin drops below vddp minus the voltage dropped across the internal boot diode. pin descriptions (continued) pin number symbol description
isl62773 9 march 7, 2012 fn8263.0 37 ugatex high-side mosfet gate driver portion of the programmable internal driver used for either channel 3 of the core vr or channel 1 of the northbridge vr based on the configuration state selected by the fccm_nb resistor. connect the ugatex pin to the gate of the high-side mosfet(s ) for either phase 3 of the core vr or phase 1 of the northbridge vr based on the configuration state selected. 38 phasex phase connection of the programmable internal dr iver used for either channel 3 of the core vr or channel 1 of the northbridge vr based on the conf iguration state selected by the fccm_nb resistor. current return path for the high-side mosfet gate dr iver of the floating internal driver. connect the phasex pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of either phase 3 of the core vr or phase 1 of the northbridge vr based on the configuration state selected. 39 lgatex low-side mosfet gate driver portion of floating internal driver used for either channel 3 of the core vr or channel 1 of the northbridge vr based on the co nfiguration state selected by the fccm_nb resistor. connect the lgatex pin to the gate of the low-side mosfet(s) for either phase 3 of the core vr or phase 1 of the northbridge vr based on the configuration state selected. 40 pwm2_nb pwm output for channel 2 of the northbri dge vr. disabled when isen2_nb is tied to +5v. 41 fccm_nb diode emulation control signal for intersil mosfet drivers. when fccm_nb is low, diode emulation at the driver this pin connects to is allowed. a resi stor from fccm_nb pin to gnd configures the pwm_y and floating internal gate driver [bootx, ugatex, phasex, lgatex pins] to support phase 3 of the core vr and phase 1 of the northbridge vr. the fccm_nb resi stor value also is used to set the slew rate for the core vr and northbridge vr. 42 pgood_nb open-drain output to indicate the northbridge portion of the ic is ready to supply regulated voltage. pull-up externally to vddp or 3.3v through a resistor. 43 comp_nb northbridge vr error amplifie r output. a resistor from comp_nb to gnd sets the northbridge vr offset voltage and is used to set the switching fr equency for the core vr and northbridge vr. 44 fb_nb output voltage feedback to the inverting in put of the northbridge controller error amplifier. 45 vsen_nb output voltage sense pin for the northbridge cont roller. connect to the +sense pin of the microprocessor die. 46 isumn_nb inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. 47 isump_nb non-inverting input of the transconductance amplifier for current monitor and load line of the northbridge vr. 48 isen1_nb individual current sensing for channel 1 of the nort hbridge vr. if isen2_nb is tied to +5v, this pin cannot be left open and must be tied to gnd with a 10k ? resistor. if isen1_nb is tied to+5v, the northbridge portion of the ic is shutdown. gnd (bottom pad) signal common of the ic. unless otherwise stated, signals are referenced to the gnd pin. pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl62773hrz isl62773 hrz -10 to +100 48 ld 6x6 qfn l48.6x6b ISL62773IRZ isl62773 irz -40 to +85 48 ld 6x6 qfn l48.6x6b notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl62773 . for more information on msl please see tech brief tb363 .
isl62773 10 march 7, 2012 fn8263.0 table of contents core performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 simplified application circuit for high power cpu core . . 2 simplified application circuit with 3 internal drivers used for core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 simplified application circuit for mid-power cpus [2+1 configuration]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 simplified application circuit for low power cpus [1+1 configuration]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .11 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 recommended operating conditions . . . . . . . . . . . . . . . . .11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 gate driver timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . .13 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 multiphase r3? modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 diode emulation and period stretching . . . . . . . . . . . . . . . . . 15 channel configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start-up timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 voltage regulation and load line implementation . . . . . . . 16 differential sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 dynamic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 fb2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 adaptive body diode conduction time reduction . . . . . . . . 20 resistor configuration options. . . . . . . . . . . . . . . . . . . . . . .20 vr offset programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 floating driverx and pwm_y configur ation. . . . . . . . . . . . . . 21 vid-on-the-fly slew rate selection . . . . . . . . . . . . . . . . . . . . . 21 ccm switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 amd serial vid interface 2.0 . . . . . . . . . . . . . . . . . . . . . . . . 21 pre-pwrok metal vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 svi interface active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 vid-on-the-fly transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 svi data communication protocol . . . . . . . . . . . . . . . . . . . . . 22 svi bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 power states and telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . 25 dynamic load line slope trim . . . . . . . . . . . . . . . . . . . . . . . . 26 dynamic offset trim. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 current-balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 thermal monitor [ntc, ntc_nb] . . . . . . . . . . . . . . . . . . . . . . . 27 fault recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 interface pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 key component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 inductor dcr current-sensing network . . . . . . . . . . . . . . . . 28 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . 30 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 load line slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 compensator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 thermal monitor component selection . . . . . . . . . . . . . . . . . 32 layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 pcb layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
isl62773 11 march 7, 2012 fn8263.0 absolute maximum rating s thermal information supply voltage, v dd, v ddp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . pha se - 0.3v (dc) to bootphase - 5v . . . . . . . . . . . . . . . . . (<20ns pulse width, 10j) to boot lgate voltage . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd + 0.3v) open drain outputs, pgood, pgood_nb, vr_hot_l. . . . . . -0.3v to +7v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 48 ld qfn package (notes 4, 5) . . . . . . . . 29 3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (plastic package) . . . . . . . . . . . .+150c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% battery voltage, v in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature hrz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c irz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c (hrz), t a = -40c to +85c (irz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -40c to +100c. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd enable = 1v 8 11 ma enable = 0v 5 a battery supply current i vin enable = 0v 1 a v in input resistance r vin enable = 1v 620 k ? power-on-reset thresholds vdd por threshold vdd_por r v dd rising 4.35 4.5 v vdd_por f v dd falling 4.00 4.15 v system and references system accuracy hrz %error (v out) no load; closed loop, active mode range, vid = 0.75v to 1.55v, -0.5 +0.5 % vid = 0.25v to 0.74375v -10 +10 mv irz %error (v out ) no load; closed loop, active mode range, vid = 0.75v to 1.55v -0.8 +0.8 % vid = 0.25v to 0.74375v -12 +12 mv maximum output voltage v out(max) vid = [00000000] 1.55 v minimum output voltage v out(min) vid = [11111111] 0.0 v channel frequency nominal channel frequency f sw(nom) 280 300 320 khz adjustment range 300 450 khz amplifiers current-sense amplifier input offset hrz i fb = 0a -0.15 +0.15 mv irz i fb = 0a -0.20 +0.20 mv error amp dc gain a v0 119 db
isl62773 12 march 7, 2012 fn8263.0 error amp gain-bandwidth product gbw c l = 20pf 17 mhz isen input bias current 20 na power-good (pgood & pgood_nb) and protection monitors pgood low voltage v ol i pgood = 4ma 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a pwrok high threshold 750 mv vr_hot_l pull-down 11 w pwrok leakage current 1 a vr_hot_l leakage current 1 a gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 w ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 w ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 w lgate source current i lgsrc lgate - vssp = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 w lgate sink current i lgsnk lgate - vssp = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns protection overvoltage threshold ov h vsen rising above setpoint for >1s 275 325 375 mv undervoltage threshold ov h vsen falls below setpoint for >1s 275 325 375 mv current imbalance threshold one isen above another isen for >1.2ms 9 mv way overcurrent trip threshold [imonx current based detection] imonx woc all states, i droop = 60ua, r imon = 135k ? 15 a overcurrent trip threshold [imonx voltage based detection] v imonx_ocp all states, i droop = 45a, i imonx = 11.25a, r imon = 135k ? 1.485 1.510 1.535 v logic thresholds enable input low v il 1 v enable input high v ih hrz 1.6 v v ih irz 1.65 v enable leakage current i enable enable = 0v -1 0 1 a enable = 1v 18 35 a svt impedance 50 w svc, svd input low v il % of vddio 30 % svc, svd input high v ih % of vddio 70 % svc, svd leakage enable = 0v, svc, svd = 0v and 1v -1 1 a enable = 1v, svc, svd = 1v -5 1 a enable = 1v, svc, svd = 0v -35 -20 -5 a pwm pwm output low v 0l sinking 5ma 1.0 v pwm output high v 0h sourcing 5ma 3.5 v pwm tri-state leakage pwm = 2.5v 0.5 a electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c (hrz), t a = -40c to +85c (irz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
isl62773 13 march 7, 2012 fn8263.0 gate driver timing diagram thermal monitor ntc source current ntc = 0.6v 27 30 33 a ntc thermal warning voltage 600 640 680 mv ntc thermal warning voltage hysteresis 20 mv ntc thermal shutdown voltage 530 580 630 mv slew rate vid-on-the-fly slew rate maximum programmed 16 20 24 mv/s minimum programmed 8 10 12 mv/s notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = -10c to +100c (hrz), t a = -40c to +85c (irz), f sw = 300khz, unless otherwise noted. boldface limits apply over the operatin g temperature range, -40c to +100c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr
isl62773 14 march 7, 2012 fn8263.0 theory of operation multiphase r 3 ? modulator the isl62773 is a multiphase regulator implementing two voltage regulators, core vr and northbridge (nb) vr, on one chip controlled by amd?s? svi2? protocol. the core vr can be programmed for 1-, 2- or 3-phase operation. the northbridge vr can be configured for 1- or 2-phas e operation. both regulators use the intersil patented r 3 ? (robust ripple regulator) modulator. the r 3 ? modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their shortcomings. figure 7 conceptually shows the multiphase r 3 ? modulator circuit, and figure 8 shows the operation principles. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the master clock signal to the slave ci rcuits. if the core vr is in 3- phase mode, the master clock signal is distributed to the three phases, and the clock 1~3 signals will be 120 out-of-phase. if the core vr is in 2-phase mode , the master clock signal is distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. if the core vr is in 1-phase mode, the master clock signal will be distri buted to phase 1 only and be the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the controller works with v crs , which are large amplitude and noise-free synthesized signals, it achieves lower phase jitter than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the error amplifier allows the isl62773 to maintain a 0.5% output voltage accuracy. figure 9 shows the operation principles during load insertion response. the comp voltage ri ses during load insertion, generating the master clock sign al more quickly, so the pwm pulses turn on earlier, increasing the effective switching frequency. this allows for higher control loop bandwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider. during load release response, th e comp voltage falls. it takes the master clock circuit longer to generate the next master clock signal so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the current pwm pulse width. this kind of behavior gives the isl62773 excellent response speed. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. figure 7. r 3 ? modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3 figure 8. r 3 ? modulator operation principles in steady state comp vcrm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 vcrs3 clock3 vcrs2 vcrs1 vw
isl62773 15 march 7, 2012 fn8263.0 diode emulation and period stretching the isl62773 can operate in diode emulation (de) mode to improve light-load efficiency. in de mode, the low-side mosfet conducts when the current is flowing from source to drain and does not allow reverse current, th us emulating a diode. figure 10 shows that when lgate is on, the low-side mosfet carries current, creating negative voltage on th e phase node due to the voltage drop across the on-resistance. th e isl62773 monitors the current by monitoring the phase node voltage. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss. if the load current is light enough, as figure 10 shows, the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm, although the controller is in de mode. figure 11 shows the operation pr inciple in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size and therefore is the same, making the inductor current triangle the same in the three cases. the isl62773 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move farther apart, su ch that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light-load efficiency. channel configuration individual pwm channels of either vr can be disabled by connecting the isenx pin of the channel not required to +5v. for example, placing the controller in a 2+1 configuration (figure 5), requires isen3 of the core vr and isen2 of the northbridge vr to be tied to +5v. this disables channel 3 of the core vr and channel 2 of the northbridge vr. isen1_nb must be tied through a 10k ? resistor to gnd to prevent this pin from pulling high and disabling the channel. connecting isen1 or isen1_nb to +5v will disable the corresponding vr output. this feature allows debug of individual vr outputs. power-on reset before the controller has suffic ient bias to guarantee proper operation, the isl62773 requires a +5v input supply tied to vdd and vddp to exceed the vdd rising power-on reset (por) threshold. once this threshold is reached or exceeded, the isl62773 has enough bias to check the state of the svi inputs once enable is taken high. hysteresis between the rising and the falling threshold on vdd por assure the isl62773 does not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications? on page 11). note that vin must be present for the controller to drive the output voltage. figure 9. r 3 ? modulator operation principles in load insertion response comp v crm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw ugate phase il lgate figure 10. diode emulation il il v crs il v crs v crs vw ccm / dcm boundary light dcm deep dcm vw vw figure 11. period stretching
isl62773 16 march 7, 2012 fn8263.0 start-up timing with vdd above the por threshold, the controller start-up sequence begins when enable ex ceeds the logic high threshold. figure 13 shows the typical soft-start timing of the core and northbridge vrs. once the controller registers enable as a high, the controller checks that state of a few programming pins during the typical 8ms delay prio r to beginning soft-starting the core and northbridge outputs. the pre-pwrok metal vid is read from the state of the svc and svd pins and programs the dac, the programming resistors on comp, comp_nb, and fccm_nb are read to configure internal drivers, switching frequency, slew rate, output offsets. these programming resistors are discussed in subsequent sections. the isl62773 uses a digital soft-start to ramp up the dac to the metal vid level programmed. the soft-start slew rate is progra mmed by the fccm_nb resistor which is used to set the vid-on-the-fly slew rate as well. see ?vid- on-the-fly slew rate selection? on page 21 for more details on selecting the fccm_nb resistor. pgood is asserted high at the end of the soft-start ramp. voltage regulation and load line implementation after the soft-start sequence, th e isl62773 regulates the output voltages to the pre-pwrok metal vid programmed, see table 6. the isl62773 controls the no-load output voltage to an accuracy of 0.5% over the range of 0.75v to 1.55v. a differential amplifier allows voltage sensing for precise voltage regulation at the microprocessor die. vdd svc svd enable pwrok v core / v core_nb 1 7 8 figure 12. svi interface timing diagram: typical pre-pwrok metal vid start-up pgood & pgood_nb 3 4 2 5 6 metal_vid v_svi interval 1 to 2: isl62773 waits to por. interval 2 to 3: svc and svd are externally set to pre-metal vid code. interval 3 to 4: enable locks pre-metal vid c ode. both outputs soft-start to this level. interval 4 to 5: pgood signal goes high, indicating proper operation. interval 6 to 7: svc and svd data lines communicate change in vid code. interval 7 to 8: isl62773 responds to vid-on-the-fly code change and issues a votf for positive vid changes. interval 5 to 6: pgood and pgood_nb high is detected and pwrok is taken high. the isl62773 is prepared for svi commands. svt telemetry telemetry votf post 8: telemetry is clocked out of the isl62773. vdd enable dac 8ms metalvid slew rate vid command voltage pgood pwrok vin figure 13. typical soft-start waveforms
isl62773 17 march 7, 2012 fn8263.0 as the load current increases from zero, the output voltage droops from the vid programmed value by an amount proportional to the load current, to achieve the load line. the isl62773 can sense the inductor current through the intrinsic dc resistance (dcr) of the induct ors (see figures 3 and 4) or through resistors in series with the inductors (see figure 5). in both methods, capacitor c n voltage represents the total inductor current. a droop amplifier converts c n voltage into an internal current source with the gain set by resistor r i . the current source is used for load line implementation, current monitoring and overcurrent protection. figure 14 shows the load-line implementation. the isl62773 drives a current source (i droop ) out of the fb pin, as described by equation 1. when using inductor dcr current sensing, a single ntc element is used to compensate the positive temperature coefficient of the copper winding, thus sustaining the load-line accuracy with reduced cost. i droop flows through resistor r droop and creates a voltage drop as shown in equation 2. v droop is the droop voltage required to implement load line. changing r droop or scaling i droop can change the load line slope. since i droop also sets the overcurrent protection level, it is recommended to first scale i droop based on ocp requirement. next, select an appropriate r droop value to obtain the desired load line slope. differential sensing figure 14 also shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the processor die. a unity ga in differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and non-inverting input voltages to be equal as shown in equation 3: rewriting equation 3 and subs tituting equation 2 gives equation 4 is the exact equation required for load-line implementation. the vcc sense and vss sense signals come from the processor die. the feedback is open circuit in the absence of the processor. as figure 14 shows, it is recommended to add a ?catch? resistor to feed the vr local output voltage back to the compensator, and to add another ?catch? resistor to connect the vr local output ground to the rtn pin. these resistors, typically 10 ? ~100 ? , provide voltage feedback if the system is powered up without a processor installed. phase current balancing the isl62773 monitors individu al phase average current by monitoring the isen1, isen2, and isen3 voltages. figure 15 shows the recommended current balancing circuit for dcr sensing. each phase node voltage is averaged by a low-pass filter consisting of r isen and c isen , and is presented to the corresponding isen pin. r isen should be routed to the inductor phase-node pad in order to eliminate the effect of phase node parasitic pcb dcr. equations 5 through 7 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output side pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the isl62773 will adjusts the phase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . figure 14. differential sensing and load line implementation x 1 e/a ? dac svid[7:0] rdroop idroop vdac vdroop fb comp vcc sense vss sense rtn vss internal to ic ?catch? resistor ?catch? resistor vr local vo + - +- + + - svc svd i droop v cn r i ---------- - = (eq. 1) v droop r droop i droop 5 4 -- - ? ?? ?? ? = (eq. 2) vcc sense v + droop v dac vss sense + = (eq. 3) vcc sense vss sense ? v dac r droop i droop 54 ? ? ?? ? ? = (eq. 4) figure 15. current balancing circuit internal to ic v o isen3 l3 r isen c isen isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr3 r dcr2 r dcr1 phase3 phase2 phase1 i l3 i l2 i l1 r pcb3 r pcb2 r pcb1 v isen1 r dcr1 r pcb1 + ?? i l1 ? = (eq. 5) v isen2 r dcr2 r pcb2 + ?? i l2 ? = (eq. 6) v isen3 r dcr3 r pcb3 + ?? i l3 ? = (eq. 7)
isl62773 18 march 7, 2012 fn8263.0 using the same components for l1, l2 and l3 provides a good match of r dcr1 , r dcr2 and r dcr3 . board layout determines r pcb1 , r pcb2 and r pcb3 . it is recommended to have a symmetrical layout for the power delivery path between each inductor and the output voltage rail, such that r pcb1 =r pcb2 =r pcb3 . at times, it is difficult to implement symmetrical layout. for the circuit shown in figure 15, asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 values, thus creating a current imbalance. figure 16 shows a differential sensing current balancing circuit recommended for isl62773. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of three sources: its ow n, phase inductor phase-node pad, and the other two phases inductor output side pads. equations 8 through 10 give the isen pin voltages: the isl62773 will make v isen1 = v isen2 = v isen3 as shown in equations 11 and 12: rewriting equation 11 gives equation 13: rewriting equation 12 gives equation 14: combining equations 13 and 14 gives: therefore: current balancing (i l1 =i l2 =i l3 ) is achieved when r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 do not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, the r 3 ? modulator can naturally achieve excellent current balancing during steady state and dynamic operations. figure 17 shows the current balancing performance of the evaluation board with load tran sient of 12a/51a at different repetition rates. the inductor currents follow the load current dynamic change with the output capacitors supplying the difference. the inductor currents can track the load current well at a low repetition rate, but canno t keep up when the repetition rate gets into the hundred-khz range, where it is out of the control loop bandwidth. the cont roller achieves excellent current balancing in all cases installed. figure 16. differential-sensing current balancing circuit internal to ic v o isen3 l3 r isen cisen isen2 r isen c isen isen1 r isen c isen l2 l1 r dcr3 r dcr2 r dcr1 phase3 phase2 phase1 i l3 i l2 i l1 r pcb3 r pcb2 r pcb1 r isen r isen r isen r isen r isen r isen v3p v 3n v2p v 2n v1p v 1n v isen1 v 1p v 2n v 3n ++ = (eq. 8) v isen2 v 1n v 2p v 3n ++ = (eq. 9) v isen3 v 1n v 2n v 3p ++ = (eq. 10) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 11) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 12) v 1p v 1n ? v 2p v 2n ? = (eq. 13) v 2p v 2n ? v 3p v 3n ? = (eq. 14) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 15) r dcr1 i l1 ? r dcr2 i l2 ? r dcr3 i l3 ? == (eq. 16)
isl62773 19 march 7, 2012 fn8263.0 modes of operation the core vr can be configured for 3, 2- or 1-phase operation. table 1 shows core vr configur ations and operational modes, programmed by the isen3 and isen2 pin status and the psl0_l and psl1_l commands via the svi 2 interface, see table 9. for a 2-phase configuration, tie the isen3 pin to 5v. in this configuration, phases 1 and 2 ar e active. to select a 1-phase configuration, tie the isen3 pin an d the isen2 pin to 5v. in this configuration, only phase-1 is active. in a 3-phase configuration, the core vr operates in 3-phase ccm, with psi0_l and psi_l both high. if psi0_l is taken low via the svi 2 interface, the core vr drops phase 3 and continues to operate in ccm. when both psi0_l and psi1_l are taken low, the core vr drops phase 2 an d enters 1-phase de mode. for 2-phase configurations, the core vr operates in 2-phase ccm with psi0_l and psi_l both high. if psi0_l is taken low via the svi 2 interface, the core vr drops phase 2 and continues to operate in 1-phase ccm. when both psi0_l and psi1_l are taken low, the core vr enters 1-phase de mode. in a 1-phase configuration, the core vr operates in 1-phase ccm and enters 1-phase de when both psi0_l and psi1_l are low. the core vr can be disabled completely by connecting isen1 to +5v. isl62773 northbridge vr can be configured for 2- or 1-phase operation. table 2 shows the northbridge vr configurations and operational modes, which are programmed by the isen2_nb pin status and the psi0_l and psi1_l bits of the svi 2 command. figure 17. current balancing during dynamic operation. ch1: i l1 , ch2: i load , ch3: i l2 , ch4: i l3 rep rate = 10khz rep rate = 25khz rep rate = 50khz rep rate = 100khz rep rate = 200khz table 1. core vr modes of operation config. isen3 isen2 psl0_l & psi1_l mode ocp threshold (a) 3-phase core vr config. to power stage to power stage 11 3-phase ccm 45 01 2-phase ccm 00 1-phase de 2-phase core vr config. tied to 5v to power stage 11 2-phase ccm 45 01 1-phase ccm 00 1-phase de 1-phase core vr config. tied to 5v tied to 5v 11 1-phase cmm 45 01 00 1-phase de table 2. northbridge vr modes of operation isen2_nb config. psl0_l & psi1_l mode ocp threshold to power stage 2-phase nb vr config. 11 2-phase ccm 45a 01 1-phase ccm 00 1-phase de tied to 5v 1-phase nb vr config. 11 1-phase ccm 45a 01 1-phase ccm 00 1-phase de
isl62773 20 march 7, 2012 fn8263.0 in a 1-phase configuration, the is en2_nb pin is tied to +5v. the northbridge vr operates in 1-phase ccm and enters 1-phase de when both psi0_l and psi1_l are low. the northbridge vr can be disabled completely by tieing isen1_nb to 5v. dynamic operation core vr and northbridge vr be have the same during dynamic operation. the controller responds to vid-on-the-fly changes by slewing to the new voltage at the slew rate programmed, see table 4. during negative vid tr ansitions, the output voltage decays to the lower vid value at the slew rate determined by the load. the r 3 ? modulator intrinsically has voltage feed-forward. the output voltage is insensitive to a fast slew rate input voltage change. fb2 function the core vr features an fb2 pin. the fb2 function is only available when the core vr is in a 2-phase configuration. figure 18 shows the fb2 function . a switch (called fb2 switch) turns on to short the fb and the fb 2 pins when the controller is in 2-phase mode. capacitors c3.1 and c3.2 are in parallel, serving as part of the compensator. when the controller enters 1-phase mode, the fb2 switch turns off, removing c3.2 and leaving only c3.1 in the compensator. the compensator gain increases with the removal of c3.2. by proper ly sizing c3.1 and c3.2, the compensator can be optimal for both 2-phase mode and 1-phase mode. when the fb2 switch is off, c3.2 is disconnected from the fb pin. however, the controller still actively drives the fb2 pin voltage to follow the fb pin voltage such th at c3.2 voltage always follows c3.1 voltage. when the controller turns on the fb2 switch, c3.2 is reconnected to the compensator smoothly. the fb2 function ensures excellent transient response in both 2-phase and 1-phase mode. if the fb2 function is not used, populate c3.1 only. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches zero. during on-time of the low-side mosfet, phase voltage is negative, and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comparator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero crossing point of the inductor current. if the inductor current has not reached zero when the low-side mosfet turns off, it will flow through the low-side mosfet bo dy diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the phase node to have a spike until it decays to zero. th e controller continues monitoring the phase voltage after turning off the low-side mosfet. to minimize the body diode-related loss, the controller also adjusts the phase comparator threshold vo ltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns. resistor configuration options the isl62773 uses the comp, comp_nb and fccm_nb pins to configure some functionality with in the ic. resistors from these pins to gnd are read during the first portion of the soft-start sequence. the following sections outline how to select the resistor values for each of these pins to correctly program the output voltage offset of each output, th e configuration of the floating driverx and pwm_y output, vid-on-the-fly slew rate, and switching frequency used for both vrs. vr offset programming a positive or negative offset is programmed for the core vr using a resistor to ground from the co mp pin and the northbridge in a similar manner from the comp_n b pin. table 3 provides the resistor value to select the desired output voltage offset r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen r1 e/a r3 c2 c1 vref r2 c3.2 c3.1 fb fb2 comp vsen controller in 2-phase mode controller in 1-phase mode figure 18. fb2 function table 3. comp and comp_nb outp ut voltage offset selection resistor value [ k ? ] comp v core offset [mv] comp_nb offset [mv] 5.62 -43.75 18.75 9.53 -37.5 31.25 13.3 -31.25 43.76 16.9 -25 50 21.0 -18.75 37.5 26.7 -12.5 25 34.0 -6.25 12.5 41.2 6.25 0 57.6 18.75 18.75 73.2 31.25 31.25 95.3 43.76 43.76 121 50 50 154 37.5 37.5 182 25 25 221 12.5 12.5 open 0 0
isl62773 21 march 7, 2012 fn8263.0 floating driverx and pwm_y configuration the isl62773 allows for one internal driver and one pwm output to be configured to opposite vrs depending on the desired configuration of the northbridge vr . internal driverx can be used as channel 1 of the northbridge vr with pwm_y used for channel 3 of the core vr. using this partitioning, a 2+1 or 1+1 configured isl62773 would not require an external driver. if routing of the driver signals would be a cause of concern due to having an internal driver on the northbridge vr, then the isl62773 can be configured to use pwm_y as channel 1 on the northbridge vr. driverx would then be used as channel 3 of the core vr. this allows the placement of the external drivers for the northbridge vr to be closer to the output stage(s) depending on the number of active phases. providing placement and layout flexibility to the northbridge vr. vid-on-the-fly slew rate selection the fccm_nb resistor is also used to select the slew rate for vid changes commanded by the proce ssor. once selected, the slew rate is locked in during soft-start and is not adjustable during operation. the lowest slew rate which can be selected is 10mv/s, which is above the minimum of 7.5mv/s required by the svi2 specification. the slew ra te selected sets the slew rate for both core and northbridge vrs, thus they cannot be independently selected. ccm switching frequency the core and northbridge vr switching frequency is set by the programming resistors on comp_nb and fccm_nc. when the isl62773 is in continuous conduc tion mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 ? modulator. as explained in the ?multiphase r3? modulator? on page 14, the effective switching frequency increases during load insertion and decreases during load release to achieve fast response. thus, the switching frequency is relatively constant at steady state. variation is expected when the power stage condition, such as input voltage, output voltage, load, etc. changes. the variation is usua lly less than 10% and does not have any significant effect on output voltage ripple magnitude. table 5 defines the switching fr equency based on the resistor values used to program the comp_nb and fccm_nb pins. use tables 3 and 4 to determine the correct resistor value in these ranges to program the desired output offset, slew rate and driverx/pwm_y configuration.t the controller monitors svi commands to determine when to enter power-saving mode, implement dynamic vid changes and shut down individual outputs. amd serial vid interface 2.0 the on-board serial vid interface 2.0 (svi 2) circuitry allows the amd processor to directly cont rol the core and northbridge voltage reference levels within the isl62773. once the pwrok signal goes high, the ic begins monitoring the svc and svd pins for instructions. the isl62773 us es a digital-to-analog converter (dac) to generate a reference voltage based on the decoded svi value. see figure 12 for a simple svi interface timing diagram. pre-pwrok metal vid typical motherboard start-up begi ns with the controller decoding the svc and svd inputs to determine the pre-pwrok metal vid setting (see table 6). once the enable input exceeds the rising threshold, the isl62773 decodes and locks the decoded value into an on-board hold register. table 4. fccm_nb resistor selection resistor value [ k ? ] slew rate for core and northbridge [mv/ ? s] driverx pwm_y 5.62 20 core vr channel 3 nb vr channel 1 9.53 15 13.3 12.5 16.9 10 21.0 20 26.7 15 34.0 12.5 41.2 10 57.6 20 nb vr channel 1 core vr channel 3 73.2 15 95.3 12.5 121 10 154 20 182 15 221 12.5 open 10 table 5. switching frequency selection frequency [khz] comp_nb range [k ? ] fccm_nb range [k ? ] 300 57.6 to open 21.0 to 41.2 or 154 to open 350 5.62 to 41.2 21.0 to 41.2 or 154 to open 400 57.6 to open 5.62 to 16.9 or 57.6 to 121 450 5.62 to 41.2 5.62 to 16.9 or 57.6 to 121
isl62773 22 march 7, 2012 fn8263.0 . once the programming pins are re ad, the internal dac circuitry begins to ramp core and northbridge vrs to the decoded pre-pwrok metal vid output level. the digital soft-start circuitry ramps the internal reference to the target gradually at a fixed rate of approximately 5mv/s un til the output voltage reaches ~250mv and then at the programmed slew rate. the controlled ramp of all output voltage planes reduces in-rush current during the soft-start interval. at the end of the soft-start interval, the pgood and pgood_nb outputs transi tion high, indicating both output planes are with in regulation limits. if the enable input falls below the enable falling threshold, the isl62773 tri-states both outp uts. pgood and pgood_nb are pulled low with the loss of enable. the core and northbridge vr output voltages decay, based on output capacitance and load leakage resistance. if bias to vd d falls below the por level, the isl62773 responds in the manner previously described. once vdd and enable rise above their respective rising thresholds, the internal dac circuitry re-acquires a pre-pwrok metal vid code, and the controller soft-starts. svi interface active once the core and northbri dge vrs have successfully soft-started and pgood and pgood _nb signals transition high, pwrok can be asserted externally to the isl62773. once pwrok is asserted to the ic, sv i instructions can begin as the controller actively monitors the svi interface. details of the svi bus protocol are provided in th e ?amd serial vid interface 2.0 (svi2) specification?. see amd publication #48022. once a vid change command is received, the isl62773 decodes the information to determine which vr is affected and the vid target is determined by the byte combinations in table 7. the internal dac circuitry steps the output voltage of the vr commanded to the new vid level. during this time, one or more of the vr outputs could be targeted. in the event either vr is commanded to power-off by serial vid commands, the pgood signal remains asserted. if the pwrok input is de-asserted , then the controller steps both the core and the northbridge vrs back to the stored pre-pwrok metal vid level in the holding register from initial soft-start. no attempt is made to read the svc and svd inputs during this time. if pwrok is re-asserted, then the isl62773 svi interface waits for instructions. if enable goes low during normal operation, all external mosfets are tri-stated and both pgood and pgood_nb are pulled low. this event clears the pre-pwrok metal vid code and forces the controller to check svc and svd upon restart, storing the pre-pwrok metal vid code found on restart. a por event on either vcc or vi n during normal operation shuts down both regulators, and both pgood outputs are pulled low. the pre-pwrok metal vid code is not retained. vid-on-the-fly transition once pwrok is high, the isl62773 detects this flag and begins monitoring the svc and svd pins for svi instructions. the microprocessor follows the protoc ol outlined in the following sections to send instructions for vid-on-the-fly transitions. the isl62773 decodes the instruction and acknowledges the new vid code. for vid codes higher than the current vid level, the isl62773 begins stepping the commanded vr outputs to the new vid target with the slew rate programmed by the fccm_nb resistor. when the vid codes are lower than the current vid level, the isl62773 checks the state of power state bits in the svi command. if power state bits are not active, the controller begins stepping the regulator output to the new vid target. if the power state bits are active, the controller allows the output voltage to decay and slowly steps the dac down with the natural decay of the output. this allows the controller to quickly recover and move to a high vid code if commanded. svi data communication protocol the svi wire protocol is based on the i 2 c bus concept. two wires [serial clock (svc) and serial data (svd)], carry information between the amd processor (master) and vr controller (slave) on the bus. the master initiates and terminates svi transactions and drives the clock, svc, during a transaction. the amd processor is always the master, and the voltage regulators are the slaves. the slave receives the svi transactions and acts accordingly. mobile svi wire protocol timing is based on high-speed mode i 2 c. see amd publication #48022 for additional details. table 6. pre-pwrok metal vid codes svc svd output voltage (v) 00 1.1 01 1.0 1 0 0.9 1 1 0.8
isl62773 23 march 7, 2012 fn8263.0 . table 7. serial vid codes svid[7:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) 0000_0000 1.55000 0010_0000 1.35000 0100_0000 1.15000 0110_0000 0.95000 0000_0001 1.54375 0010_0001 1.34375 0100_0001 1.14375 0110_0001 0.94375 0000_0010 1.53750 0010_0010 1.33750 0100_0010 1.13750 0110_0010 0.93750 0000_0011 1.53125 0010_0011 1.33125 0100_0011 1.13125 0110_0011 0.93125 0000_0100 1.52500 0010_0100 1.32500 0100_0100 1.12500 0110_0100 0.92500 0000_0101 1.51875 0010_0101 1.31875 0100_0101 1.11875 0110_0101 0.91875 0000_0110 1.51250 0010_0110 1.31250 0100_0110 1.11250 0110_0110 0.91250 0000_0111 1.50625 0010_0111 1.30625 0100_0111 1.10625 0110_0111 0.90625 0000_1000 1.50000 0010_1000 1.30000 0100_1000 1.10000 0110_1000 0.90000 0000_1001 1.49375 0010_1001 1.29375 0100_1001 1.09375 0110_1001 0.89375 0000_1010 1.48750 0010_1010 1.28750 0100_1010 1.08750 0110_1010 0.88750 0000_1011 1.48125 0010_1011 1.28125 0100_1011 1.08125 0110_1011 0.88125 0000_1100 1.47500 0010_1100 1.27500 0100_1100 1.07500 0110_1100 0.87500 0000_1101 1.46875 0010_1101 1.26875 0100_1101 1.06875 0110_1101 0.86875 0000_1110 1.46250 0010_1110 1.26250 0100_1110 1.06250 0110_1110 0.86250 0000_1111 1.45625 0010_1111 1.25625 0100_1111 1.05625 0110_1111 0.85625 0001_0000 1.45000 0011_0000 1.25000 0101_0000 1.05000 0111_0000 0.85000 0001_0001 1.44375 0011_0001 1.24375 0101_0001 1.04375 0111_0001 0.84375 0001_0010 1.43750 0011_0010 1.23750 0101_0010 1.03750 0111_0010 0.83750 0001_0011 1.43125 0011_0011 1.23125 0101_0011 1.03125 0111_0011 0.83125 0001_0100 1.42500 0011_0100 1.22500 0101_0100 1.02500 0111_0100 0.82500 0001_0101 1.41875 0011_0101 1.21875 0101_0101 1.01875 0111_0101 0.81875 0001_0110 1.41250 0011_0110 1.21250 0101_0110 1.01250 0111_0110 0.81250 0001_0111 1.40625 0011_0111 1.20625 0101_0111 1.00625 0111_0111 0.80625 0001_1000 1.40000 0011_1000 1.20000 0101_1000 1.00000 0111_1000 0.80000 0001_1001 1.39375 0011_1001 1.19375 0101_1001 0.99375 0111_1001 0.79375 0001_1010 1.38750 0011_1010 1.18750 0101_1010 0.98750 0111_1010 0.78750 0001_1011 1.38125 0011_1011 1.18125 0101_1011 0.98125 0111_1011 0.78125 0001_1100 1.37500 0011_1100 1.17500 0101_1100 0.97500 0111_1100 0.77500 0001_1101 1.36875 0011_1101 1.16875 0101_1101 0.96875 0111_1101 0.76875 0001_1110 1.36250 0011_1110 1.16250 0101_1110 0.96250 0111_1110 0.76250 0001_1111 1.35625 0011_1111 1.15625 0101_1111 0.95625 0111_1111 0.75625 1000_0000 0.75000 1010_0000 0.55000* 1100_0000 0.35000* 1110_0000 0.15000* 1000_0001 0.74375 1010_0001 0.54375* 1100_0001 0.34375* 1110_0001 0.14375* 1000_0010 0.73750 1010_0010 0.53750* 1100_0010 0.33750* 1110_0010 0.13750* 1000_0011 0.73125 1010_0011 0.53125* 1100_0011 0.33125* 1110_0011 0.13125* 1000_0100 0.72500 1010_0100 0.52500* 1100_0100 0.32500* 1110_0100 0.12500* 1000_0101 0.71875 1010_0101 0.51875* 1100_0101 0.31875* 1110_0101 0.11875* 1000_0110 0.71250 1010_0110 0.51250* 1100_0110 0.31250* 1110_0110 0.11250* 1000_0111 0.70625 1010_0111 0.50625* 1100_0111 0.30625* 1110_0111 0.10625*
isl62773 24 march 7, 2012 fn8263.0 1000_1000 0.70000 1010_1000 0.50000* 1100_1000 0.30000* 1110_1000 0.10000* 1000_1001 0.69375 1010_1001 0.49375* 1100_1001 0.29375* 1110_1001 0.09375* 1000_1010 0.68750 1010_1010 0.48750* 1100_1010 0.28750* 1110_1010 0.08750* 1000_1011 0.68125 1010_1011 0.48125* 1100_1011 0.28125* 1110_1011 0.08125* 1000_1100 0.67500 1010_1100 0.47500* 1100_1100 0.27500* 1110_1100 0.07500* 1000_1101 0.66875 1010_1101 0.46875* 1100_1101 0.26875* 1110_1101 0.06875* 1000_1110 0.66250 1010_1110 0.46250* 1100_1110 0.26250* 1110_1110 0.06250* 1000_1111 0.65625 1010_1111 0.45625* 1100_1111 0.25625* 1110_1111 0.05625* 1001_0000 0.65000 1011_0000 0.45000* 1101_0000 0.25000* 1111_0000 0.05000* 1001_0001 0.64375 1011_0001 0.44375* 1101_0001 0.24375* 1111_0001 0.04375* 1001_0010 0.63750 1011_0010 0.43750* 1101_0010 0.23750* 1111_0010 0.03750* 1001_0011 0.63125 1011_0011 0.43125* 1101_0011 0.23125* 1111_0011 0.03125* 1001_0100 0.62500 1011_0100 0.42500* 1101_0100 0.22500* 1111_0100 0.02500* 1001_0101 0.61875 1011_0101 0.41875* 1101_0101 0.21875* 1111_0101 0.01875* 1001_0110 0.61250 1011_0110 0.41250* 1101_0110 0.21250* 1111_0110 0.01250* 1001_0111 0.60625 1011_0111 0.40625* 1101_0111* 0.20625* 1111_0111 0.00625* 1001_1000 0.60000* 1011_1000 0.40000* 1101_1000 0.20000* 1111_1000 off* 1001_1001 0.59375* 1011_1001 0.39375* 1101_1001 0.19375* 1111_1001 off* 1001_1010 0.58750* 1011_1010 0.38750* 1101_1010 0.18750* 1111_1010 off* 1001_1011 0.58125* 1011_1011 0.38125* 1101_1011 0.18125* 1111_1011 off* 1001_1100 0.57500* 1011_1100 0.37500* 1101_1100 0.17500* 1111_1100 off* 1001_1101 0.56875* 1011_1101 0.36875* 1101_1101 0.16875* 1111_1101 off* 1001_1110 0.56250* 1011_1110 0.36250* 1101_1110 0.16250* 1111_1110 off* 1001_1111 0.55625* 1011_1111 0.35625* 1101_1111 0.15625* 1111_1111 off* notes: 7. * indicates a vid not required for amd family 10h processors 8. * loosened amd requiremen ts at this levels. table 7. serial vid codes (continued) svid[7:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v) svid[6:0] voltage (v)
isl62773 25 march 7, 2012 fn8263.0 svi bus protocol the amd processor bus protocol is compliant with smbus send byte protocol for vid transactions. the amd svd packet structure is shown in figure 19. the description of what each bit of the three bytes that make up the sv i command are shown in table 8. during a transaction, the proc essor sends the start sequence followed by each of the three bytes, which end with an optional acknowledge bit. the isl62773 does not drive the svd line during the ack bit. finally, the processor sends the stop sequence. after the isl62773 has detected the stop, it can then proceed with the commanded action from the transaction. power states and telemetry svi2 defines two power state indicator levels, see table 9. as processor current consumption is reduces the power state indicator level increases starting with 0. for the core vr operating in 3-phase mode, when psi0_l is asserted channel 3 is tri-stated to boost efficiency. when psi1_l is asserted, channel 2 is tri-st ated and channel 1 enters diode emulation mode to further boost efficiency. in 2-phase mode, when psi0_l is asserted, cha nnel 2 is tri-stated. asserting psi1_l in this mode results in channel 1 entering diode emulation mode. for the northbridge vr operating in 2-phase mode, when psi0_l is asserted channel 2 is tri-stated to boost efficiency. when psi1_l is asserted channel 1 enters diode emulation mode to further boost efficiency. it is possible for the processor to assert or deassert psi0_l and psi1_l out of order. psi0_l takes priority over psi1_l. if psi0_l is deasserted while psi1_l is still asserted, the isl62773 will return the selected vr back full channel ccm operation. the tfn bit along with the core and northbridge domain selector bits are used by the processor to change the functionality of telemetry, see table 10 for more information. figure 19. svd packet structure 1 23 45 67 12 14 15 16 17 13 10 svd svc start psi1_l vid bits [7:1] 11 8 9 18 19 20 21 22 23 24 25 26 27 vid bit [0] psi0_l ack ack ack table 8. svd data packet bits description 1:5 always 11000b 6 core domain selector bit, if se t then the following data byte contains vid, power state, telemetry control, load line trim and offset trim apply to the core vrwer4444. 7 northbridge domain selector bit, if set then the following data byte contains vid, power state, telemetry control, load line trim and offset trim apply to the northbridge vr. 8always 0b 9acknowledge bit 10 psi0_l 11:17 vid code bits [7:1] 18 acknowledge bit 19 vid code bit [0] 20 psi1_l 21 tfn (telemetry functionality) 22:24 load line slope trim 25:26 offset trim [1:0] 27 acknowledge bit table 9. psi0_l, psi1_l and tfn definition function bit description psi0_l 10 power state indicate level 0. when this signal is asserted (active low) the processor is in a low enough power state for the isl62773 to take action to boost efficiency by dropping phases. psi1_l 20 power state indicate level 1. when this signal is asserted (active low) the processor is in a low enough power state for the isl62773 to take additional action to boost efficiency beyond that taken with psi0_l asserted. tfn 21 telemetry functionality. th is is an active high signal that allows the processor to control the telemetry functionality of the vr. table 10. tfn truth table tfn, core, nb bits [21,6,7] description 1,0,1 telemetry is in voltage and current mode. therefore, voltage and current are sent for vdd and vddnb domains by the controller. 1,0,0 telemetry is in voltage mode only. only the voltage of vdd and vddnb domains is sent by the controller. 1,1,0 telemetry is disabled. 1,1,1 reserved
isl62773 26 march 7, 2012 fn8263.0 dynamic load line slope trim the isl62773 supports the svi2 ability for the processor to manipulate the load line slope of the core and northbridge vrs independently using the serial vid interface. the slope manipulation applies to the initial load line slope. a load line slope trim will typically coincide with a votf change. refer to table 11 for more information ab out the load line slope trim feature of the isl62773. dynamic offset trim the isl62773 supports the svi2 ability for the processor to manipulate the output voltage offset of the core and northbridge vrs. this offset is in addition to any output voltage offset set via the comp resistor reader. the dy namic offset trim can disable the comp resistor programmed of fset of either output when disable all offset? is selected. protection features core vr and northbridge vr both provide overcurrent, current-balance, undervoltage, an d overvoltage fault protections. the controller also provides ov er-temperature protection. the following discussion is based on core vr and also applies to the northbridge vr. overcurrent overcurrent protection is trigge red when the voltage across the imon resistor is 1.5v. within 2s of detecting the imon voltage, the controller asserts vr_hot_l low to communicate to the amd cpu to throttle back. a fault timer begins counting while imon is at or above the 1.5v threshold. the fault timer lasts 7.5s to 11s and then flags an ocp fault. the controller then tri-states the active channels and goes into shutdown. pgood is taken low and a fault flag from this vr is sent to the other vr and it is shutdown within 10s. if the imon voltage drops below the 1.5v threshold prior to the fault timer count fini shing, the fault timer is cleared and vr_hot_l is taken high. the isl62773 also features a wa y-overcurrent [woc] feature, which immediately takes the controller into shutdown. this protection is also referred to as fast overcurrent protection for short-circuit protection. if the imon current reaches 15a, woc is triggered. active channels are tri-stated and the controller is placed in shutdown and pgood is pulled low. there is no fault timer on the woc fault, the contro ller takes immediate action. the other controller output is also shutdown within 10s. designing the current feedback components and setting the ocp level require knowing the iddspike value (edc) outlined for the amd cpu under consideration. am d specifications will outline a tdc current level and an edc curr ent level for each cpu. the edc current is the maximum current the cpu can demand for a short, thermally insignificant time. when selecting the components for the current feedback design or using an intersil design spreadsheet, the edc current is us ed as the full load current. the reasoning is that the amd cpu will view reaching the edc current as 100% loading. the desired droop current at full load must be set to 45a. the controller generates a current across the imon resistor that is ? of the average value of the isum current. the droop current is 5/4 greater than the isum current, so for a droop current of 45a the isum curre nt is 36a. the recommended imon resistor value is 133k ? , 1% tolerance. at full load current, edc level, the resulting imon voltage will be 1.2v and telemetry will report 100%. if the load current continues to increase, then the imon voltage will continue to rise, but the telemetry will still report 100% loading. once the isum current reaches 45a, the corresponding current out of the imon pin is 11.25a and the voltage on the imon resistor will be 1.5v and the controller will report an oc trip. the load current at this point is 25% higher than the edc current used for setting full load droop current. this additional margin allows the amd cpu to enter and exit the iddspike performance mode without issue unless the load current is out of line with the iddspike expectation. current-balance the controller monitors the isenx pin voltages to determine current-balance protection. if the isenx pin voltage difference is greater than 9mv for 1ms, the controller will declare a fault and latch off. undervoltage if the vsen voltage falls below th e output voltage vid value plus any programmed offsets by -325mv, the controller declares an undervoltage fault. the controller de-asserts pgood and tri-states the power mosfets. overvoltage if the vsen voltage exceeds the ou tput voltage vid value plus any programmed offsets by +325mv, the controller declares an overvoltage fault. the controller de-asserts pgood and turns on the low-side power mosfets. the low- side power mosfets remain on until the output voltage is pulled down below the vid set value. once the output voltage is below this leve l, the lower gate is tri-stated. if the output voltage rises above the overvoltage threshold again, the protection process is repeated when all power mosfets are turned off. this behavior provides th e maximum amount of protection against shorted high-side power mo sfets while preventing output ringing below ground. table 11. load line slope trim definition load line slope trim [2:0] description 000 disable ll 001 -40% m ? change 010 -20% m ? change 011 no change 100 +20% m ? change 101 +40% m ? change 110 +60% m ? change 111 +80% m ? change table 12. offset trim definition offset trim [1:0] description 00 disable all offset 01 -25mv change 10 0mv change? 11 +25mv change
isl62773 27 march 7, 2012 fn8263.0 thermal monitor [ntc, ntc_nb] the isl62773 features two thermal monitors which use an external resistor network which includes an ntc thermistor to monitor motherboard temperature and alert the amd cpu of a thermal issue. figure 20 shows the basic thermal monitor circuit on the core vr ntc pin. the no rthbridge vr features the same thermal monitor. the controller drives a 30a current out of the ntc pin and monitors the voltage at the pin. the current flowing out of the ntc pin creates a voltage that is compared to a warning threshold of 640mv. when the voltage at the ntc pin falls to this warning threshold or below, the controller asserts vr_hot_l to alert the amd cpu to throttle back load current to stabilize the motherboard temperature. a thermal fault counter begins counting toward a minimum shutdown time of 100s. the thermal fault counter is an up/down counter, so if the voltage at the ntc pin rises abov e the warning threshold, it will count down and extend the time for a thermal fault to occur. the warning threshold does have 20mv of hysteresis. if the voltage at the ntc pin continues to fall down to the shutdown threshold of 580mv or below, the controller goes into shutdown and triggers a thermal fault. the pgood pin is pulled low and tri-states the power mosfet s. a fault on either side will shutdown both vrs. as the board temperature rises, the ntc thermistor resistance decreases and the voltage at the ntc pin drops. when the voltage on the ntc pin drops below the over-temperature trip threshold, then vr_hot is pulled low. the vr_hot signal is used to change the cpu operation an d decrease power consumption. with the reduction in power cons umption by the cpu, the board temperature decreases and the nt c thermistor voltage rises. once the over-temperature threshold is tripped and vr_hot is taken low, the over-temperature threshold changes to the reset level. the addition of hysteresis to the over-temperature threshold prevents nuisance trips. once both pin voltages exceed the over-temperature reset thresh old, the pull-down on vr_hot is released. the signal chan ges state and th e cpu resumes normal operation. the over-tempe rature threshold returns to the trip level. table 13 summarizes th e fault protections. fault recovery all of the previously described fa ult conditions can be reset by bringing enable low or by bringing vdd below the por threshold. when enable and vdd return to their high operating levels, the controller resets the faults and soft-start occurs. interface pin protection the svc and svd pins feature protection diodes which must be considered when removing power to vdd and vddio, but leaving it applied to these pins. figure 21 shows the basic protection on the pins. if svc and/or svd are powered but vdd is not, leakage current will flow from these pins to vdd. ntc r ntc v ntc - + 30a internal to isl62773 figure 20. circuitry associated with the thermal monitor feature of the isl62773 r s monitor r +v r p warning 640mv shutdown 580mv vr_hot_l table 13. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 7.5s to 11.5s pwm tri-state, pgood latched low enable toggle or vdd toggle phase current unbalance 1ms way-overcurrent (1.5xoc) immediately undervoltage -325mv pgood latched low. pwm tri-state. overvoltage +325mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. ntc thermal 100s min pgood latched low. pwm tri-state. svc, svd internal to isl62773 figure 21. protection devices on the svc and svd pins gnd vdd
isl62773 28 march 7, 2012 fn8263.0 key component selection inductor dcr current-sensing network figure 22 shows the inductor dcr current-sensing network for a 3-phase solution. an inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors in r sum and r o connected to the pads to a ccurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to temperature compensate the inductor dcr change. the inductor output side pads are electrically shorted in the schematic but have some parasi tic impedance in actual board layout, which is why one cannot simply short them together for the current-sensing summing network. it is recommended to use 1 ? ~10 ?? r o to create quality signals. since r o value is much smaller than the rest of the current sensing circuit, the following analysis ignores it. the summed inductor current information is presented to the capacitor c n . equations 17 thru 21 describe the frequency domain relationship between inductor total current i o (s) and c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher reading of the inductor dc current. the ntc r ntc value decrease as its temperature decreases. proper selection of r sum , r ntcs , r p and r ntc parameters ensures that v cn represents the inductor total dc current over the temperature range of interest. there are many sets of parameters that can properly temperature-compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. it is recommended to have a higher ratio of v cn to the inductor dcr voltage so the droop circuit has a higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k ? , r p =11k ? , r ntcs = 2.61k ? and r ntc = 10k ? (ert-j1vr103j). the ntc network parameters may need to be fine tuned on actual boards. one can apply full load dc current and record the output voltage reading immediately; then record the ou tput voltage reading again when the board has reached the thermal steady state. a good ntc network can limit the output voltag e drift to within 2mv. it is recommended to follow the intersil evaluation board layout and current sensing network parameters to minimize engineering time. v cn (s) also needs to represent real-time i o (s) for the controller to achieve good transient response. transfer function a cs (s) has a pole w sns and a zero w l . one needs to match w l and w sns so a cs (s) is unity gain at all frequencies. by forcing w l equal to w sns and solving for the solution, equation 22 gives cn value. for example, given n = 3, r sum = 3.65k ? , r p = 11k ? , r ntcs =2.61k ? , r ntc = 10k ? , dcr = 0.88m ? and l = 0.36h, equation 22 gives c n = 0.406f. assuming the compensator design is correct, figure 23 shows the expected load transient response waveforms if c n is correctly selected. when the load current i core has a square change, the output voltage v core also has a square response. if c n value is too large or too small, v cn (s) does not accurately represent real-time i o (s) and worsens the transient response. figure 24 shows the load transient response when c n is too small. v core sags excessively upon load insertion and may create a system failure. figure 25 shows the transient response when c n is too large. v core is sluggish in drooping to its final value. there is excessive overshoot if load insertion occurs during this time, which may negatively affect the cpu reliability. cn r sum r o r ntcs r ntc r p dcr l dcr l r sum r o phase2 phase3 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn + - figure 22. dcr current-sensing network v cn s ?? r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ? ?? ?? ?? ?? ?? i o s ?? ? a cs ? s ?? = (eq. 17) r ntcnet r ntcs r ntc + ?? r p ? r ntcs r ntc r p ++ ---------------------------------------------------- = (eq. 18) a cs s ?? 1 s ? l ------ - + 1 s ? sns ------------ - + ---------------------- - = (eq. 19) ? l dcr l ------------- = (eq. 20) ? sns 1 r ntcnet r sum n -------------- - ? r ntcnet r sum n -------------- - + ------------------------------------------ c n ? -------------------------------------------------------- = (eq. 21) c n l r ntcnet r sum n -------------- - ? r ntcnet r sum n -------------- - + ------------------------------------------ dcr ? -------------------------------------------------------------- - = (eq. 22)
isl62773 29 march 7, 2012 fn8263.0 figure 26 shows the output vo ltage ring-back problem during load transient response. the load current i o has a fast step change, but the inductor current i l cannot accurately follow. instead, i l responds in first-order system fashion due to the nature of the current loop. the esr and esl effect of the output capacitors makes the output voltage v o dip quickly upon load current change. however, the controller regulates v o according to the droop current i droop , which is a real-time representation of i l ; therefore, it pulls v o back to the level dictated by i l , causing the ring-back problem. this phenomen on is not observed when the output capacitor has very low esr and esl, as is the case with all ceramic capacitors. figure 27 shows two optional circuits for reduction of the ring-back. c n is the capacitor used to match the inductor time constant. it usually takes the parallel of two (or more) capacitors to get the desired value. figure 27 shows that two capacitors (c n.1 and c n.2 ) are in parallel. resistor r n is an optional component to reduce the v o ring-back. at steady state, c n.1 + c n.2 provides the desired c n capacitance. at the beginning of i o change, the effective capacitance is less because r n increases the impedance of the c n.1 branch. as figure 24 shows, v o tends to dip when c n is too small, and this effect reduces the v o ring-back. this effect is more pronounced when c n.1 is much larger than c n.2 . it is also more pronounced when r n is bigger. however, the presence of r n increases the ripple of the v n signal if c n.2 is too small. it is recommended to keep c n.2 greater than 2200pf. the r n value usually is a few ohms. c n.1 , c n.2 and r n values should be determined through tuning the load transient response waveforms on an actual board. r ip and c ip form an r-c branch in parallel with r i , providing a lower impedance path than r i at the beginning of i o change. r ip and c ip do not have any effect at steady state. through proper selection of r ip and c ip values, i droop can resemble i o rather than i l , and v o will not ring back. the recommended value for r ip is 100 ? . c ip should be determined through tuning the load transient response waveforms on an actual board. the recommended range for c ip is 100pf~2000pf. however, it should be noted that the r ip -c ip branch may distort the i droop waveform. instead of being triangular as the real inductor current, i droop may have sharp spikes, which may adversely affect i droop average value detection and therefore may affect ocp accuracy. user discretion is advised. figure 23. desired load transient response waveforms o i v o figure 24. load transient response when c n is too small o i v o figure 25. load transient response when c n is too large o i v o figure 26. output voltage ring-back problem o i v o l i ring back figure 27. optional circuits for ring-back reduction cn.2 rntcs rntc rp ri isum+ isum- rip cip optional vcn cn.1 rn optional
isl62773 30 march 7, 2012 fn8263.0 resistor current-sensing network figure 28 shows the resistor current-sensing network for a 3-phase solution. each inductor has a series current sensing resistor, r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 23 thru 25 give the v cn (s) expression. transfer function a rsen (s) always has unity gain at dc. current-sensing resistor r sen value does not have significant variation over-temperature, so there is no need for the ntc network. the recommended values are r sum = 1k ? and c n = 5600pf. overcurrent protection refer to equation 1 on page 17 and figures 22, 26 and 28; resistor r i sets the droop current, i droop . tables 1 and 2 show the internal ocp threshold. it is recommended to design i droop without using the r comp resistor. for example, the ocp threshold is 1.5v on the imon pin. this translates to 45a of i sum current or 56.25a of droop current. i droop is designed to be 45a at full load, so the ocp trip level is 1.25x of the full load current. for inductor dcr sensing, equation 26 gives the dc relationship of v cn (s) and i o (s): substitution of equation 26 into equation 1 gives equation 27: therefore: substitution of equation 18 and application of the ocp condition in equation 28 gives equation 29: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 3, r sum = 3.65k ? , r p = 11k ? , r ntcs = 2.61k ? , r ntc = 10k ? , dcr = 0.9m ? , i omax = 65a and i droopmax = 45a. equation 29 gives r i = 359 ? . for resistor sensing, equation 30 gives the dc relationship of v cn (s) and i o (s). substitution of equation 30 into equation 1 gives equation 31: therefore: substitution of equation 32 and application of the ocp condition in equation 28 gives equation 33: where i omax is the full load current and i droopmax is the corresponding droop current. for example, given n = 3, r sen =1m ? , i omax = 65a and i droopmax = 45a, equation 33 gives r i = 481 ?? load line slope see figure 14 for load-line implementation. for inductor dcr sensing, substitution of equation 27 into equation 2 gives the load-line slope expression in equation 34: for resistor sensing, substitution of equation 31 into equation 2 gives the load line slope expression in equation 35: figure 28. resistor current-sensing network cn r sum r o dcr l dcr l r sum r o phase2 phase3 i o dcr l phase1 r o r sum ri i sum+ i sum- vcn rsen rsen rsen + - v cn s ?? r sen n ------------- i o s ?? ? a rsen ? s ?? = (eq. 23) a rsen s ?? 1 1 s ? sns ------------ - + ---------------------- - = (eq. 24) ? rsen 1 r sum n -------------- - c n ? ---------------------------- - = (eq. 25) v cn r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ? ?? ?? ?? ?? ?? i o ? = (eq. 26) i droop 1 r i ----- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ? ? i o ? = (eq. 27) r i r ntcnet dcr ? i o ? nr ntcnet r sum n -------------- - + ?? ?? ? i droop ? --------------------------------------------------------------------------------- - = (eq. 28) r i r ntcs r ntc + ?? r p ? r ntcs r ntc r p ++ ---------------------------------------------------- dcr ? i omax ? n r ntcs r ntc + ?? r p ? r ntcs r ntc r p ++ ---------------------------------------------------- r sum n -------------- - + ?? ?? ?? ? i droopmax ? ---------------------------------------------------------------------------------------------------------------------------- - = (eq. 29) v cn r sen n ------------- i o ? = (eq. 30) i droop 1 r i ----- r sen n ------------- i o ? ? = (eq. 31) r i r sen i o ? ni droop ? --------------------------- = (eq. 32) r i r sen i omax ? ni droopmax ? -------------------------------------- = (eq. 33) ll v droop i o ------------------ - r droop r i ------------------- r ntcnet r ntcnet r sum n -------------- - + ------------------------------------------ dcr n ------------- ? ? == (eq. 34) ll v droop i o ------------------ - r sen r droop ? nr i ? --------------------------------------- == (eq. 35)
isl62773 31 march 7, 2012 fn8263.0 substitution of equation 28 and rewriting equation 34, or substitution of equation 32 and rewriting equation 35, gives the same result as in equation 36: one can use the full-load condition to calculate r droop . for example, given i omax = 65a, i droopmax = 45a and ll = 2.1m ? , equation 36 gives r droop = 3.03k ? . it is recommended to start with the r droop value calculated by equation 36 and fine-tune it on the actual board to get accurate load-line slope. one should record the output voltage readings at no load and at full load for load -line slope calculation. reading the output voltage at lighter load instead of full load will increase the measurement error. compensator figure 23 shows the desired load transient response waveforms. figure 29 shows the equivalent circuit of a voltage regulator (vr) with the droop function. a vr is equivalent to a voltage source (= vid) and output impedance z out (s). if z out (s) is equal to the load-line slope ll, i.e., a constant output impedance, then in the entire frequency range, v o will have a square response when i o has a square change. intersil provides a microsoft excel-based spreadsheet to help design the compensator and the cu rrent sensing network so that vr achieves constant output impedance as a stable system. a vr with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop. however, neither loop alone is sufficient to describe the entire system. the spreadsheet shows two loop gain transfer functions, t1(s) and t2(s), that describe the entire system. figure 30 conceptually shows t1(s) measurement set-up, and figure 31 conceptually shows t2(s) measurement set-up. the vr senses the inductor current, multiplies it by a gain of the load-line slope, adds it on top of the sensed output voltage, and then feeds it to the compensator. t1 is measured af ter the summing node, and t2 is measured in the voltage loop before the summing node. the spreadsheet gives both t1(s) and t2(s) plots. however, only t2(s) can actually be measured on an isl62773 regulator. t1(s) is the total loop gain of the voltage loop and the droop loop. it always has a higher crossover frequency than t2(s), therefore has a higher impact on system stability. t2(s) is the voltage loop gain with closed droop l oop, thus having a higher impact on output voltage response. design the compensator to get stable t1(s) and t2(s) with sufficient phase margin and an output impedance equal to or smaller than the load-line slope. current balancing refer to figures 15 through 22 for information on current balancing. the isl62773 achieves current balancing through matching the isen pin voltages. r isen and c isen form filters to remove the switching ripple of the phase node voltages. it is recommended to use a rather long r isen c isen time constant such that the isen voltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k ? and c s =0.22f. r droop i o i droop ---------------- ll ? = (eq. 36) figure 29. voltage regulator equivalent circuit o i v o vid z out (s) = ll load vr figure 30. loop gain t1(s) measurement set-up q2 q1 l i o c out v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 [ loop gain = channel b channel a network analyzer + + + - ? figure 31. loop gain t2(s) measurement set-up q2 q1 l i o c o v o v in gate driver comp mod. load line slope ea vid channel b channel a excitation output isolation transformer 20 loop gain = channel b channel a network analyzer + + + - ?
isl62773 32 march 7, 2012 fn8263.0 thermal monitor component selection the isl62773 features two pins, ntc and ntc_nb, which are used to monitor motherboard temperature and alert the amd cpu if a thermal issues arises. the basic function of this circuitry is outlined in the ?thermal monitor [ntc, ntc_nb]? on page 27. figure 32 shows the basic configuration of the ntc resistor, r ntc , and offset resistor, r s , used to generate the warning and shutdown voltages at the ntc pin. as the board temperature rises, the ntc thermistor resistance decreases and the voltage at the ntc pin drops. when the voltage on the ntc pin drops below the thermal warning threshold of 0.640v, then vr_hot_l is pulled low. when the amd cpu detects that vr_hot_l has gone low, it will begin throttling back load current on bo th outputs to reduce the board temperature. if the board temperature continues to rise, the ntc thermistor resistance will drop further and the voltage at the ntc pin could drop below the thermal shutdown threshold of 0.580v. once this threshold is reached, the isl62773 shuts down both core and northbridge vrs indicating a ther mal fault has occurred prior to the thermal fault counter triggering a fault. selection of the ntc thermistor can vary depending on how the resistor network is configured. th e equivalent resistance at the typical thermal warning threshold voltage of 0.64v is defined in equation 37. the equivalent resistance at the typical thermal shutdown threshold voltage of 0.58v required to shutdown both outputs is defined in equation 38. the ntc thermistor value correlates to the resistance change between the warning and shutdown thresholds and the required temperature change. if the warning level is designed to occur at a board temperature of +100c and the thermal shutdown level at a board temperature of +105c, th en the resistance change of the thermistor can be calculated. for example, a panasonic ntc thermistor with b = 4700 has a resi stance ratio of 0.03939 of its nominal value at +100c and 0.03308 of its nominal value at +105c. taking the required re sistance change between the thermal warning threshold and the shutdown threshold and dividing it by the change in resi stance ratio of the ntc thermistor at the two temperatures of interest, the required resistance of the ntc is defined in equation 39. the closest standard thermistor to the value calculated with b = 4700 is 330k ? . the ntc thermistor part number is ertj0ev334j. the actual resistan ce change of this standard thermistor value between the warning threshold and the shutdown threshold is calculated in equation 40. since the ntc thermist or resistance at +105c is less than the required resistance from equation 38, additional resistance in series with the thermistor is requ ired to make up the difference. a standard resistor, 1% toleranc e, added in series with the thermistor will increase the voltage seen at the ntc pin. the additional resistance required is calculated in equation 41. the closest, standard 1% tolerance resistor is 8.45k ? . the ntc thermistor is placed in a hot spot on the board, typically near the upper mosfet of channe l 1 of the respective output. the standard resistor is pl aced next to the controller. layout guidelines pcb layout considerations power and signal layers placement on the pcb as a general rule, power layers should be close together, either on the top or bottom of the board, with the weak analog or logic signal layers on the opposite side of the board. the ground-plane layer should be adjacent to the signal layer to provide shielding. component placement there are two sets of critical components in a dc/dc converter; the power components and the small signal components. the power components are the most critical because they switch large amount of energy. the small signal components connect to sensitive nodes or supply critic al bypassing current and signal coupling. the power components should be placed first and these include mosfets, input and output capacitors, and the inductor. it is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each power train. symmetrical layout allows heat to be dissipated equally across all power trains. keeping the distance between ntc r ntc 30a internal to isl62773 figure 32. thermal monitor feature of the isl62773 r s monitor r +v warning 640mv shutdown 580mv vr_hot_l 330k ? 8.45k ? 0.64v 30 ? a --------------- - 21.3k ? = (eq. 37) 0.58v 30 ? a --------------- - 19.3k ? = (eq. 38) 21.3k ? 19.3k ? ? ?? 0.03939 0.03308 ? ?? ----------------------------------------------------- - 317k ? = (eq. 39) 330k ? 0.03939 ? ?? 330k ? 0.03308 ? ?? ? 2.082k ? = (eq. 40) 19.3k ? 10.916k ? ? 8.384k ? = (eq. 41)
isl62773 33 march 7, 2012 fn8263.0 the power train and the control ic short helps keep the gate drive traces short. these drive signals include the lgate, ugate, pgnd, phase and boot. when placing mosfets, try to keep the source of the upper mosfets and the drain of the lower mosfets as close as thermally possible (see figure 33). input high-frequency capacitors should be placed close to the drain of the upper mosfets and the source of the lower mosfets. place the output inductor and output capacitors between the mosfets and the load. high-frequency output decoupling capacitors (ceramic) should be placed as close as possible to the decoupling target (microprocessor), making use of the shortest connection paths to any internal planes. place the components in such a way that the area under the ic has less noise traces with high dv/dt and di/dt, such as gate signals and phase node signals. table 14 shows layout considerations for the isl62773 controller by pin. figure 33. typical power component placement inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets table 14. layout considerations for the isl62773 controller pin number symbol layout guidelines bottom pad gnd connect this ground pad to the ground plane through a low impedance path. a minimum of 5 vias are recommended to connect this pad to the in ternal ground plane layers of the pcb 1 isen2_nb each isen pin has a capacitor (cisen) decoupling it to vsumn_nb, then through another capacitor (cvsumn_nb) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. isen1_nb pin to isen2_nb pin 2. any isenx_nb pin to gnd 2 ntc_nb the ntc thermistor must be placed close to the th ermal source that is monitored to determine northbridge thermal throttling. placement at the hottest spot of th e northbridge vr is recomme nded. additional standard resistors in the resistor network on this pin should be placed near the ic. 3 imon_nb place the imon_nb resistor close to this pin and make keep a tight gnd connection. 4 svc use good signal integrity practi ces and follow amd recommendations. 5 vr_hot_l follow amd recommendations. placement of the pull-up resistor near the ic is recommended. 6 svd use good signal integrity practi ces and follow amd recommendations. 7 vddio use good signal integrity prac tices and follow amd recommendations. 8 svt use good signal integrity practi ces and follow amd recommendations. 9 enable no special considerations. 10 pwrok use good signal integrity prac tices and follow amd recommendations. 11 imon place the imon resistor close to this pin and make keep a tight gnd connection. 12 ntc the ntc thermistor must be placed close to the ther mal source that is monitored to determine core thermal throttling. placement at the hottest spot of the core vr is recommended. additional standard resistors in the resistor network on this pin should be placed near the ic.
isl62773 34 march 7, 2012 fn8263.0 13 isen3 each isen pin has a capacitor (c isen ) decoupling it to vsumn and then through another capacitor (c vsumn ) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops to be minimized. 14 isen2 15 isen1 16 isump place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to core vr channel 1 indu ctor so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum p and vsumn signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer an d use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing th e traces into the pads from the inside of the inductor. the following drawings show the two preferre d ways of routing current sensing traces. 17 isumn 18 vsen place the filter on these pins in close proximity to the controller for good coupling. 19 rtn 20 fb2 place the compensation components in general proximity of the controller. 21 fb 22 comp 23 pgood no special consideration. 24 boot1 use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 25 ugate1 these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive analog signal traces or crossing over them. routing phase1 to the core vr channel 1 high-side mosfet so urce pin instead of a general connection to phase1 copper is recommended for better performance. 26 phase1 table 14. layout considerations for th e isl62773 controller (continued) pin number symbol layout guidelines v o isen3 l3 risen isen2 isen1 l2 l1 risen risen phase1 phase2 phase3 ro ro ro gnd cisen cisen cisen cvsumn vsumn inductor current-sensing traces vias inductor current-sensing traces
isl62773 35 march 7, 2012 fn8263.0 27 lgate1 use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. 28 pwm_y no special considerations. 29 vdd a high quality, x7r dielectric mlcc capacitor is reco mmended to decouple this pin to gnd. place the capacitor in close proximity to the pin with the filter resistor nearby the ic. 30 vddp a high quality, x7r dielectric mlcc capacitor is reco mmended to decouple this pin to gnd. place the capacitor in close proximity to the pin. 31 lgate2 use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. 32 phase2 these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive analog signal traces or crossing over them. routing phase2 to the core vr channel 2 high-side mosfet so urce pin instead of a general connection to phase2 copper is recommended for better performance. 33 ugate2 34 boot2 use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 35 vin place the decoupling capacitor in close proximity to the pin with a short connection to the internal gnd plane. 36 bootx use a wide trace width (>30mil). avoid routing any sensit ive analog signal traces clos e to or crossing over this trace. 37 ugatex these two signals should be routed together in parallel. each trace should have sufficient width (>30mil). avoid routing these signals near sensitive anal og signal traces or crossing over them. routing phasex to the high-side mosfet source pin instead of a general connection to the phasex copper is recommended for better performance. 38 phasex 39 lgatex use sufficient trace width (>30mil). avoid routing this signal near any sensitive analog signal traces or crossing over them. 40 pwm2_nb no special considerations. 41 fccm_nb 42 pgood_nb no special consideration. 43 comp_nb place the compensation components in general proximity of the controller. 44 fb_nb 45 vsen_nb place the filter on this pin in close proximity to the controller for good coupling. 46 isumn_nb place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to core vr channel 1 indu ctor so it senses the inductor temperature correctly. each phase of the power stage sends a pair of vsum p and vsumn signals to the controller. run these two signals traces in parallel fashion with decent width (>20mil). important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer an d use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing th e traces into the pads from the inside of the inductor. the following drawings show the two preferre d ways of routing current sensing traces. 47 isump_nb 48 isen1_nb table 14. layout considerations for th e isl62773 controller (continued) pin number symbol layout guidelines inductor current-sensing traces vias inductor current-sensing traces
isl62773 36 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com march 7, 2012 fn8263.0 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl62773 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 7, 2012 fn8263.0 initial release
isl62773 37 march 7, 2012 fn8263.0 package outline drawing l48.6x6b 48 lead quad flat no-lead plastic package rev 0, 9/09 typical recommended land pattern detail "x" side view top view bottom view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 6.00 a b pin 1 index area (4x) 0.15 6 6.00 4.4 37 44x 0.40 4x pin #1 index area 48 6 4 .40 0.15 1 ab 48x 0.45 0.10 24 13 48x 0.20 4 0.10 c m 36 25 12 max 1.00 seating plane base plane 5 c 0 . 2 ref 0 . 00 min. 0 . 05 max. 0.10 c 0.08 c c see detail "x" ( 5. 75 typ ) ( 4. 40 ) ( 48x 0 . 20 ) ( 48x 0 . 65 ) ( 44 x 0 . 40 ) 0.05 m c

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